Created H Bridge Repo master
Created H Bridge Repo

file:b/makefile (new)
--- /dev/null
+++ b/makefile
@@ -1,1 +1,26 @@
 
+.PHONY: build
+
+build: create-dirs all
+
+all: gerb/H_Bridge_Gerb.zip
+
+create-dirs:
+	mkdir -p gerb
+
+gerb/H_Bridge_Gerb.zip:
+	pcb -x gerber --gerberfile gerb/H_Bridge schem/H_Bridge.pcb
+	mv gerb/H_Bridge.group1.gbr		gerb/H_Bridge.GBL
+	mv gerb/H_Bridge.top.gbr			gerb/H_Bridge.GTL
+	mv gerb/H_Bridge.bottommask.gbr	gerb/H_Bridge.GBS
+	mv gerb/H_Bridge.topmask.gbr		gerb/H_Bridge.GTS
+	mv gerb/H_Bridge.bottomsilk.gbr	gerb/H_Bridge.GBO
+	mv gerb/H_Bridge.topsilk.gbr		gerb/H_Bridge.GTO
+	mv gerb/H_Bridge.outline.gbr		gerb/H_Bridge.GKO
+	mv gerb/H_Bridge.plated-drill.cnc	gerb/H_Bridge.XLN
+	zip gerb/H_Bridge_Gerb.zip gerb/H_Bridge.GBL gerb/H_Bridge.GTL gerb/H_Bridge.GBS gerb/H_Bridge.GTS gerb/H_Bridge.GBO gerb/H_Bridge.GTO gerb/H_Bridge.GKO gerb/H_Bridge.XLN
+	rm gerb/H_Bridge.*
+
+clean:
+	rm -rf gerb
+

--- /dev/null
+++ b/schem/H_Bridge.net
@@ -1,1 +1,11 @@
+unnamed_net9	Q2-1 R2-1 
+unnamed_net8	IN-2 R2-2 
+unnamed_net7	Q1-1 R1-1 
+unnamed_net6	IN-1 R1-2 
+unnamed_net5	Q5-1 Q6-1 Q2-3 R5-1 R6-2 
+unnamed_net4	Q3-1 Q1-3 Q4-1 R3-1 R4-2 
+GND	Q2-2 Q1-2 C1-2 VIN-2 R6-1 Q6-3 D4-1 Q4-3 R4-1 D2-1 
+unnamed_net3	C1-1 VIN-1 R3-2 R5-2 Q5-3 D3-2 Q3-3 D1-2 
+unnamed_net2	D4-2 D3-1 Q5-2 Q6-2 OUT-2 
+unnamed_net1	D1-1 D2-2 Q3-2 Q4-2 OUT-1 
 

--- /dev/null
+++ b/schem/H_Bridge.pcb
@@ -1,1 +1,1346 @@
-
+# release: pcb 20110918
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20070407]
+
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+
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+	Line[72086 40000 74586 42500 1000 2000 "clearline"]
+	Line[74586 42500 74586 73500 1000 2000 "clearline"]
+	Line[74586 73500 72586 75500 1000 2000 "clearline"]
+	Line[72586 82500 124586 82500 1000 2000 "clearline"]
+	Line[124586 82500 155586 51500 1000 2000 "clearline"]
+	Line[155586 51500 155586 46000 1000 2000 "clearline"]
+	Line[155586 46000 154586 45000 1000 2000 "clearline"]
+	Line[154586 45000 148586 45000 1000 2000 "clearline"]
+	Line[148586 45000 147086 43500 1000 2000 "clearline"]
+	Line[137586 80000 137586 81000 2500 2000 "clearline"]
+	Line[137586 81000 141586 81000 1000 2000 "clearline"]
+	Line[141586 81000 146586 86000 1000 2000 "clearline"]
+	Line[146586 86000 181086 86000 1000 2000 "clearline"]
+	Line[181086 86000 188586 93500 1000 2000 "clearline"]
+)
+Layer(3 "signal2")
+(
+)
+Layer(4 "signal3")
+(
+)
+Layer(5 "power")
+(
+)
+Layer(6 "bottom")
+(
+)
+Layer(7 "outline")
+(
+	Line[0 120000 220000 120000 1000 2000 "clearline"]
+	Line[220000 120000 220000 0 1000 2000 "clearline"]
+	Line[220000 0 0 0 1000 2000 "clearline"]
+	Line[0 0 0 120000 1000 2000 "clearline"]
+)
+Layer(8 "spare")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+)
+NetList()
+(
+	Net("GND" "(unknown)")
+	(
+		Connect("C1-2")
+		Connect("D2-1")
+		Connect("D4-1")
+		Connect("Q1-2")
+		Connect("Q2-2")
+		Connect("Q4-3")
+		Connect("Q6-3")
+		Connect("R4-1")
+		Connect("R6-1")
+		Connect("VIN-2")
+	)
+	Net("unnamed_net1" "(unknown)")
+	(
+		Connect("D1-1")
+		Connect("D2-2")
+		Connect("OUT-1")
+		Connect("Q3-2")
+		Connect("Q4-2")
+	)
+	Net("unnamed_net2" "(unknown)")
+	(
+		Connect("D3-1")
+		Connect("D4-2")
+		Connect("OUT-2")
+		Connect("Q5-2")
+		Connect("Q6-2")
+	)
+	Net("unnamed_net3" "(unknown)")
+	(
+		Connect("C1-1")
+		Connect("D1-2")
+		Connect("D3-2")
+		Connect("Q3-3")
+		Connect("Q5-3")
+		Connect("R3-2")
+		Connect("R5-2")
+		Connect("VIN-1")
+	)
+	Net("unnamed_net4" "(unknown)")
+	(
+		Connect("Q1-3")
+		Connect("Q3-1")
+		Connect("Q4-1")
+		Connect("R3-1")
+		Connect("R4-2")
+	)
+	Net("unnamed_net5" "(unknown)")
+	(
+		Connect("Q2-3")
+		Connect("Q5-1")
+		Connect("Q6-1")
+		Connect("R5-1")
+		Connect("R6-2")
+	)
+	Net("unnamed_net6" "(unknown)")
+	(
+		Connect("IN-1")
+		Connect("R1-2")
+	)
+	Net("unnamed_net7" "(unknown)")
+	(
+		Connect("Q1-1")
+		Connect("R1-1")
+	)
+	Net("unnamed_net8" "(unknown)")
+	(
+		Connect("IN-2")
+		Connect("R2-2")
+	)
+	Net("unnamed_net9" "(unknown)")
+	(
+		Connect("Q2-1")
+		Connect("R2-1")
+	)
+)
+

--- /dev/null
+++ b/schem/H_Bridge.sch
@@ -1,1 +1,688 @@
+v 20130925 2
+T 42100 47400 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 42100 48000 5 10 0 0 0 0 1
+description=NMOS transistor
+T 42100 47800 5 10 0 0 0 0 1
+numslots=0
+T 42100 47600 5 10 0 0 0 0 1
+symversion=0.1
+T 43900 47000 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 45200 46600 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 45200 46600 5 10 0 0 0 0 1
+numslots=0
+T 45200 46600 5 10 0 0 0 0 1
+description=generic N channel MOS transistor (enhancement type)
+N 43300 46000 43300 46600 4
+N 40100 46000 40100 46600 4
+C 42300 47500 1 90 0 connector2-2.sym
+{
+T 41000 48200 5 10 1 1 90 6 1
+refdes=OUT
+T 41050 47800 5 10 0 0 90 0 1
+device=CONNECTOR_2
+T 42500 47700 5 10 1 1 90 0 1
+footprint=GSIP2
+}
+N 40100 46300 41500 46300 4
+N 41500 46300 41500 47500 4
+N 43300 46300 41900 46300 4
+N 41900 46300 41900 47500 4
+C 40700 46500 1 90 0 diode-1.sym
+{
+T 40100 46900 5 10 0 0 90 0 1
+device=DIODE
+T 40700 47000 5 10 1 1 0 0 1
+refdes=D1
+T 40700 46600 5 10 1 1 0 0 1
+footprint=ACY300P
+T 40700 46800 5 10 1 1 0 0 1
+device=1N4001
+}
+C 43100 46500 1 90 0 diode-1.sym
+{
+T 42500 46900 5 10 0 0 90 0 1
+device=DIODE
+T 42000 47000 5 10 1 1 0 0 1
+refdes=D3
+T 42000 46600 5 10 1 1 0 0 1
+footprint=ACY300P
+T 42000 46800 5 10 1 1 0 0 1
+device=1N4001
+}
+C 40700 45100 1 90 0 diode-1.sym
+{
+T 40100 45500 5 10 0 0 90 0 1
+device=DIODE
+T 40800 45700 5 10 1 1 0 0 1
+refdes=D2
+T 40800 45500 5 10 1 1 0 0 1
+device=1N4001
+T 40800 45300 5 10 1 1 0 0 1
+footprint=ACY300P
+}
+C 43100 45100 1 90 0 diode-1.sym
+{
+T 42500 45500 5 10 0 0 90 0 1
+device=DIODE
+T 41900 45700 5 10 1 1 0 0 1
+refdes=D4
+T 41900 45500 5 10 1 1 0 0 1
+device=1N4001
+T 41900 45300 5 10 1 1 0 0 1
+footprint=ACY300P
+}
+N 40500 46300 40500 46000 4
+N 40500 46300 40500 46500 4
+N 40100 47400 40100 48500 4
+N 36900 48500 44700 48500 4
+N 40500 48500 40500 47400 4
+N 42900 47400 42900 48500 4
+N 43300 47400 43300 48500 4
+C 40000 43100 1 0 0 gnd-1.sym
+N 40100 43400 40100 45200 4
+N 40100 44000 44700 44000 4
+N 40500 44000 40500 45100 4
+N 42900 45100 42900 44000 4
+N 43300 45200 43300 44000 4
+N 42900 46500 42900 46300 4
+N 42900 46300 42900 46000 4
+C 38900 44300 1 90 0 resistor-1.sym
+{
+T 38500 44600 5 10 0 0 90 0 1
+device=RESISTOR
+T 39000 44900 5 10 1 1 0 0 1
+refdes=R4
+T 39000 44500 5 10 1 1 0 0 1
+value=10K
+T 39000 44700 5 10 1 1 0 0 1
+footprint=0805
+}
+C 44800 44300 1 90 0 resistor-1.sym
+{
+T 44400 44600 5 10 0 0 90 0 1
+device=RESISTOR
+T 44900 44900 5 10 1 1 0 0 1
+refdes=R6
+T 44900 44700 5 10 1 1 0 0 1
+footprint=0805
+T 44900 44500 5 10 1 1 0 0 1
+value=10K
+}
+C 44800 47400 1 90 0 resistor-1.sym
+{
+T 44400 47700 5 10 0 0 90 0 1
+device=RESISTOR
+T 44900 48000 5 10 1 1 0 0 1
+refdes=R5
+T 44900 47800 5 10 1 1 0 0 1
+footprint=0805
+T 44900 47600 5 10 1 1 0 0 1
+value=10K
+}
+C 38900 47400 1 90 0 resistor-1.sym
+{
+T 38500 47700 5 10 0 0 90 0 1
+device=RESISTOR
+T 39000 48000 5 10 1 1 0 0 1
+refdes=R3
+T 39000 47800 5 10 1 1 0 0 1
+footprint=0805
+T 39000 47600 5 10 1 1 0 0 1
+value=1K
+}
+C 36600 46200 1 180 0 resistor-1.sym
+{
+T 36300 45800 5 10 0 0 180 0 1
+device=RESISTOR
+T 35800 46300 5 10 1 1 180 0 1
+refdes=R1
+T 35900 46300 5 10 1 1 0 0 1
+footprint=0805
+T 35500 45900 5 10 1 1 0 0 1
+value=10K
+}
+C 36600 43900 1 180 0 resistor-1.sym
+{
+T 36300 43500 5 10 0 0 180 0 1
+device=RESISTOR
+T 35800 44000 5 10 1 1 180 0 1
+refdes=R2
+T 35900 44000 5 10 1 1 0 0 1
+footprint=0805
+T 35500 43600 5 10 1 1 0 0 1
+value=10K
+}
+N 38800 44000 40100 44000 4
+N 38800 44000 38800 44300 4
+N 44700 44000 44700 44300 4
+N 44700 45200 44700 47400 4
+N 44700 45400 43800 45400 4
+N 38800 45200 38800 47400 4
+N 38800 45400 39600 45400 4
+N 37400 47200 38800 47200 4
+N 43800 47200 44700 47200 4
+N 44700 48300 44700 48500 4
+N 38800 48500 38800 48300 4
+C 37300 42800 1 0 0 gnd-1.sym
+N 37400 43100 37400 43300 4
+C 37300 45100 1 0 0 gnd-1.sym
+N 37400 45600 37400 45400 4
+N 37400 46600 37400 47200 4
+N 36600 46100 36800 46100 4
+N 36600 43800 36800 43800 4
+N 37400 44300 37400 44500 4
+N 37400 44500 38600 44500 4
+N 38600 44500 38600 42900 4
+N 38600 42900 45400 42900 4
+N 45400 42900 45400 45400 4
+N 45400 45400 44700 45400 4
+C 35000 44400 1 0 1 connector2-2.sym
+{
+T 34300 45700 5 10 1 1 180 8 1
+refdes=IN
+T 34700 45650 5 10 0 0 180 2 1
+device=CONNECTOR_2
+T 34200 44200 5 10 1 1 0 0 1
+footprint=GSIP2
+}
+N 35000 45200 35200 45200 4
+N 35200 45200 35200 46100 4
+N 35200 46100 35700 46100 4
+N 35700 43800 35200 43800 4
+N 35200 43800 35200 44800 4
+N 35000 44800 35200 44800 4
+C 36900 47700 1 0 1 connector2-2.sym
+{
+T 36200 49000 5 10 1 1 180 8 1
+refdes=VIN
+T 36600 48950 5 10 0 0 180 2 1
+device=CONNECTOR_2
+T 36100 47500 5 10 1 1 0 0 1
+footprint=GSIP2
+}
+C 37000 47600 1 0 0 gnd-1.sym
+N 37100 47900 37100 48100 4
+N 36900 48100 37300 48100 4
+C 38200 48300 1 180 0 capacitor-2.sym
+{
+T 38000 47600 5 10 0 0 180 0 1
+device=POLARIZED_CAPACITOR
+T 37900 48200 5 10 1 1 0 0 1
+refdes=C1
+T 38000 47400 5 10 0 0 180 0 1
+symversion=0.1
+T 37500 47700 5 10 1 1 0 0 1
+value=1000 uF
+T 36800 48200 5 10 1 1 0 0 1
+footprint=RCY200P
+}
+N 38200 48100 38400 48100 4
+N 38400 48100 38400 48500 4
+N 38800 47200 39600 47200 4
+T 35000 45300 9 10 1 0 0 0 1
+A
+T 35000 44500 9 10 1 0 0 0 1
+B
+T 34300 47700 9 10 1 0 0 0 1
+A
+T 34600 47700 9 10 1 0 0 0 1
+B
+T 35000 47700 9 10 1 0 0 0 1
+Out
+T 34300 47400 9 10 1 0 0 0 1
+0
+T 34600 47100 9 10 1 0 0 0 1
+1
+T 35000 47400 9 10 1 0 0 0 1
++ +
+T 35000 47100 9 10 1 0 0 0 1
++ -
+T 35000 46800 9 10 1 0 0 0 1
+- +
+T 35000 46500 9 10 1 0 0 0 1
+- -
+T 34600 47400 9 10 1 0 0 0 1
+0
+T 34300 47100 9 10 1 0 0 0 1
+0
+T 34600 46800 9 10 1 0 0 0 1
+0
+T 34300 46800 9 10 1 0 0 0 1
+1
+T 34300 46500 9 10 1 0 0 0 1
+1
+T 34600 46500 9 10 1 0 0 0 1
+1
+B 34200 46400 1200 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+C 39600 45200 1 0 0 EMBEDDEDNMOS.sym
+[
+L 39850 45800 40100 45800 3 0 0 0 -1 -1
+L 39850 45400 40100 45400 3 0 0 0 -1 -1
+L 39850 45600 39950 45650 3 0 0 0 -1 -1
+L 39850 45600 39950 45550 3 0 0 0 -1 -1
+P 39600 45400 39800 45400 1 0 0
+{
+T 39705 45445 5 10 0 1 0 6 1
+pinnumber=1
+T 39855 45395 9 10 0 1 0 0 1
+pinlabel=G
+T 39600 45500 5 10 0 0 0 0 1
+pinseq=1
+T 39600 45500 5 10 0 0 0 0 1
+pintype=pas
+T 39600 45400 5 10 0 0 0 0 1
+pintype=unknown
+T 39855 45395 5 10 0 1 0 0 1
+pinlabel=unknown
+T 39705 45445 5 10 0 1 0 6 1
+pinnumber=0
+T 39600 45400 5 10 0 0 0 0 1
+pinseq=0
+}
+P 40100 45800 40100 46000 1 0 1
+{
+T 40050 45895 5 10 0 1 90 0 1
+pinnumber=2
+T 40100 45745 9 10 0 1 90 6 1
+pinlabel=D
+T 39900 45900 5 10 0 0 0 0 1
+pinseq=2
+T 39900 45900 5 10 0 0 0 0 1
+pintype=pas
+T 40100 45800 5 10 0 0 0 0 1
+pintype=unknown
+T 40100 45745 5 10 0 1 90 6 1
+pinlabel=unknown
+T 40050 45895 5 10 0 1 90 0 1
+pinnumber=0
+T 40100 45800 5 10 0 0 0 0 1
+pinseq=0
+}
+P 40100 45400 40100 45200 1 0 1
+{
+T 40050 45305 5 10 0 1 90 6 1
+pinnumber=3
+T 40100 45455 9 10 0 1 90 0 1
+pinlabel=S
+T 39900 45200 5 10 0 0 0 0 1
+pinseq=3
+T 39900 45200 5 10 0 0 0 0 1
+pintype=pas
+T 40100 45400 5 10 0 0 0 0 1
+pintype=unknown
+T 40100 45455 5 10 0 1 90 0 1
+pinlabel=unknown
+T 40050 45305 5 10 0 1 90 6 1
+pinnumber=0
+T 40100 45400 5 10 0 0 0 0 1
+pinseq=0
+}
+L 39850 45875 39850 45725 3 0 0 0 -1 -1
+L 39850 45675 39850 45525 3 0 0 0 -1 -1
+L 39850 45475 39850 45325 3 0 0 0 -1 -1
+L 39800 45800 39800 45400 3 0 0 0 -1 -1
+L 39850 45600 40000 45600 3 0 0 0 -1 -1
+L 40000 45600 40000 45400 3 0 0 0 -1 -1
+T 40200 45700 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 40200 45700 5 10 0 0 0 0 1
+numslots=0
+T 40200 45700 5 10 0 0 0 0 1
+description=generic N channel MOS transistor (enhancement type)
+T 40200 45800 8 10 0 1 0 0 1
+refdes=Q?
+]
+{
+T 40200 45700 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 38900 45900 5 10 1 1 0 0 1
+refdes=Q4
+T 38900 45700 5 10 1 1 0 0 1
+device=RFP30N05
+T 38900 45500 5 10 1 1 0 0 1
+footprint=TO220W
+}
+C 36800 45600 1 0 0 EMBEDDEDNPN.sym
+[
+P 37400 46600 37400 46400 1 0 0
+{
+T 37300 46450 5 6 1 1 0 0 1
+pinnumber=3
+T 37300 46450 5 6 0 0 0 0 1
+pinseq=3
+T 37300 46450 5 6 0 1 0 0 1
+pinlabel=3
+T 37300 46450 5 6 0 1 0 0 1
+pintype=pas
+}
+P 37400 45800 37400 45600 1 0 1
+{
+T 37300 45650 5 6 1 1 0 0 1
+pinnumber=2
+T 37300 45650 5 6 0 0 0 0 1
+pinseq=2
+T 37300 45650 5 6 0 1 0 0 1
+pinlabel=2
+T 37300 45650 5 6 0 1 0 0 1
+pintype=pas
+}
+V 37300 46101 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 37400 45800 37200 46000 3 0 0 0 -1 -1
+L 37400 46400 37200 46200 3 0 0 0 -1 -1
+L 37200 46300 37200 45900 3 0 0 0 -1 -1
+P 36800 46100 36984 46100 1 0 0
+{
+T 36900 46150 5 6 1 1 0 0 1
+pinnumber=1
+T 36900 46150 5 6 0 0 0 0 1
+pinseq=1
+T 36900 46150 5 6 0 1 0 0 1
+pinlabel=1
+T 36900 46150 5 6 0 1 0 0 1
+pintype=pas
+}
+L 37200 46100 36984 46100 3 0 0 0 -1 -1
+H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5
+M 37310,45840
+L 37401,45800
+L 37355,45895
+L 37335,45865
+z
+T 37700 46100 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 37700 46100 8 10 0 1 0 0 1
+refdes=Q?
+]
+{
+T 37700 46100 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 37700 46300 5 10 1 1 0 0 1
+refdes=Q1
+T 37700 46100 5 10 1 1 0 0 1
+device=2N2222A
+T 37700 45900 5 10 1 1 0 0 1
+footprint=SOT23
+}
+C 36800 43300 1 0 0 EMBEDDEDNPN.sym
+[
+P 37400 44300 37400 44100 1 0 0
+{
+T 37300 44150 5 6 1 1 0 0 1
+pinnumber=3
+T 37300 44150 5 6 0 0 0 0 1
+pinseq=3
+T 37300 44150 5 6 0 1 0 0 1
+pinlabel=3
+T 37300 44150 5 6 0 1 0 0 1
+pintype=pas
+}
+P 37400 43500 37400 43300 1 0 1
+{
+T 37300 43350 5 6 1 1 0 0 1
+pinnumber=2
+T 37300 43350 5 6 0 0 0 0 1
+pinseq=2
+T 37300 43350 5 6 0 1 0 0 1
+pinlabel=2
+T 37300 43350 5 6 0 1 0 0 1
+pintype=pas
+}
+V 37300 43801 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 37400 43500 37200 43700 3 0 0 0 -1 -1
+L 37400 44100 37200 43900 3 0 0 0 -1 -1
+L 37200 44000 37200 43600 3 0 0 0 -1 -1
+P 36800 43800 36984 43800 1 0 0
+{
+T 36900 43850 5 6 1 1 0 0 1
+pinnumber=1
+T 36900 43850 5 6 0 0 0 0 1
+pinseq=1
+T 36900 43850 5 6 0 1 0 0 1
+pinlabel=1
+T 36900 43850 5 6 0 1 0 0 1
+pintype=pas
+}
+L 37200 43800 36984 43800 3 0 0 0 -1 -1
+H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5
+M 37310,43540
+L 37401,43500
+L 37355,43595
+L 37335,43565
+z
+T 37700 43800 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 37700 43800 8 10 0 1 0 0 1
+refdes=Q?
+]
+{
+T 37700 43800 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 37700 44000 5 10 1 1 0 0 1
+refdes=Q2
+T 37700 43800 5 10 1 1 0 0 1
+device=2N2222A
+T 37700 43600 5 10 1 1 0 0 1
+footprint=SOT23
+}
+C 43800 45200 1 0 1 EMBEDDEDNMOS.sym
+[
+L 43550 45800 43300 45800 3 0 0 0 -1 -1
+L 43550 45400 43300 45400 3 0 0 0 -1 -1
+L 43550 45600 43450 45650 3 0 0 0 -1 -1
+L 43550 45600 43450 45550 3 0 0 0 -1 -1
+P 43800 45400 43600 45400 1 0 0
+{
+T 43695 45445 5 10 0 1 0 0 1
+pinnumber=1
+T 43545 45395 9 10 0 1 0 6 1
+pinlabel=G
+T 43800 45500 5 10 0 0 0 6 1
+pinseq=1
+T 43800 45500 5 10 0 0 0 6 1
+pintype=pas
+T 43800 45400 5 10 0 0 0 6 1
+pintype=unknown
+T 43545 45395 5 10 0 1 0 6 1
+pinlabel=unknown
+T 43695 45445 5 10 0 1 0 0 1
+pinnumber=0
+T 43800 45400 5 10 0 0 0 6 1
+pinseq=0
+}
+P 43300 45800 43300 46000 1 0 1
+{
+T 43350 45895 5 10 0 1 90 2 1
+pinnumber=2
+T 43300 45745 9 10 0 1 90 8 1
+pinlabel=D
+T 43500 45900 5 10 0 0 0 6 1
+pinseq=2
+T 43500 45900 5 10 0 0 0 6 1
+pintype=pas
+T 43300 45800 5 10 0 0 0 6 1
+pintype=unknown
+T 43300 45745 5 10 0 1 90 8 1
+pinlabel=unknown
+T 43350 45895 5 10 0 1 90 2 1
+pinnumber=0
+T 43300 45800 5 10 0 0 0 6 1
+pinseq=0
+}
+P 43300 45400 43300 45200 1 0 1
+{
+T 43350 45305 5 10 0 1 90 8 1
+pinnumber=3
+T 43300 45455 9 10 0 1 90 2 1
+pinlabel=S
+T 43500 45200 5 10 0 0 0 6 1
+pinseq=3
+T 43500 45200 5 10 0 0 0 6 1
+pintype=pas
+T 43300 45400 5 10 0 0 0 6 1
+pintype=unknown
+T 43300 45455 5 10 0 1 90 2 1
+pinlabel=unknown
+T 43350 45305 5 10 0 1 90 8 1
+pinnumber=0
+T 43300 45400 5 10 0 0 0 6 1
+pinseq=0
+}
+L 43550 45875 43550 45725 3 0 0 0 -1 -1
+L 43550 45675 43550 45525 3 0 0 0 -1 -1
+L 43550 45475 43550 45325 3 0 0 0 -1 -1
+L 43600 45800 43600 45400 3 0 0 0 -1 -1
+L 43550 45600 43400 45600 3 0 0 0 -1 -1
+L 43400 45600 43400 45400 3 0 0 0 -1 -1
+T 43200 45700 5 10 0 0 0 6 1
+device=NMOS_TRANSISTOR
+T 43200 45700 5 10 0 0 0 6 1
+numslots=0
+T 43200 45700 5 10 0 0 0 6 1
+description=generic N channel MOS transistor (enhancement type)
+T 43200 45800 8 10 0 1 0 6 1
+refdes=Q?
+]
+{
+T 43200 45700 5 10 0 0 0 6 1
+device=NMOS_TRANSISTOR
+T 43700 45900 5 10 1 1 0 0 1
+refdes=Q6
+T 43700 45700 5 10 1 1 0 0 1
+device=RFP30N05
+T 43700 45500 5 10 1 1 0 0 1
+footprint=TO220W
+}
+C 39600 47400 1 180 1 EMBEDDEDPMOS.sym
+[
+L 39850 46800 40100 46800 3 0 0 0 -1 -1
+L 39850 47200 40100 47200 3 0 0 0 -1 -1
+L 39900 47050 40000 47000 3 0 0 0 -1 -1
+L 39900 46950 40000 47000 3 0 0 0 -1 -1
+P 39600 47200 39800 47200 1 0 0
+{
+T 39600 47100 5 10 0 1 0 2 1
+pinnumber=1
+T 39600 47100 9 10 0 1 0 2 1
+pinlabel=1
+T 39600 47100 5 10 0 0 0 2 1
+pinseq=1
+T 39600 47100 5 10 0 0 0 2 1
+pintype=pas
+}
+P 40100 46800 40100 46600 1 0 1
+{
+T 39900 46700 5 10 0 1 0 2 1
+pinnumber=2
+T 39900 46700 9 10 0 1 0 2 1
+pinlabel=2
+T 39900 46700 5 10 0 0 0 2 1
+pinseq=2
+T 39900 46700 5 10 0 0 0 2 1
+pintype=pas
+}
+P 40100 47200 40100 47400 1 0 1
+{
+T 39900 47400 5 10 0 1 0 2 1
+pinnumber=3
+T 39900 47400 9 10 0 1 0 2 1
+pinlabel=3
+T 39900 47400 5 10 0 0 0 2 1
+pinseq=3
+T 39900 47400 5 10 0 0 0 2 1
+pintype=pas
+}
+L 39850 46725 39850 46875 3 0 0 0 -1 -1
+L 39850 46925 39850 47075 3 0 0 0 -1 -1
+L 39850 47125 39850 47275 3 0 0 0 -1 -1
+L 39800 46800 39800 47200 3 0 0 0 -1 -1
+L 39850 47000 40000 47000 3 0 0 0 -1 -1
+L 40000 47000 40000 47200 3 0 0 0 -1 -1
+T 40200 46900 5 10 0 0 0 2 1
+device=PMOS_TRANSISTOR
+T 40200 46900 5 10 0 0 0 2 1
+numslots=0
+T 40200 46900 5 10 0 0 0 2 1
+description=generic P channel MOS transistor (enhancement type)
+T 40300 46800 8 10 0 1 0 2 1
+refdes=Q?
+]
+{
+T 40200 46900 5 10 0 0 0 2 1
+device=PMOS_TRANSISTOR
+T 39100 46700 5 10 1 1 180 8 1
+refdes=Q3
+T 39100 46500 5 10 1 1 0 0 1
+device=RFP30P05
+T 39100 46300 5 10 1 1 0 0 1
+footprint=TO220W
+}
+C 43800 47400 1 180 0 EMBEDDEDPMOS.sym
+[
+L 43550 46800 43300 46800 3 0 0 0 -1 -1
+L 43550 47200 43300 47200 3 0 0 0 -1 -1
+L 43500 47050 43400 47000 3 0 0 0 -1 -1
+L 43500 46950 43400 47000 3 0 0 0 -1 -1
+P 43800 47200 43600 47200 1 0 0
+{
+T 43800 47100 5 10 0 1 0 8 1
+pinnumber=1
+T 43800 47100 9 10 0 1 0 8 1
+pinlabel=1
+T 43800 47100 5 10 0 0 0 8 1
+pinseq=1
+T 43800 47100 5 10 0 0 0 8 1
+pintype=pas
+}
+P 43300 46800 43300 46600 1 0 1
+{
+T 43500 46700 5 10 0 1 0 8 1
+pinnumber=2
+T 43500 46700 9 10 0 1 0 8 1
+pinlabel=2
+T 43500 46700 5 10 0 0 0 8 1
+pinseq=2
+T 43500 46700 5 10 0 0 0 8 1
+pintype=pas
+}
+P 43300 47200 43300 47400 1 0 1
+{
+T 43500 47400 5 10 0 1 0 8 1
+pinnumber=3
+T 43500 47400 9 10 0 1 0 8 1
+pinlabel=3
+T 43500 47400 5 10 0 0 0 8 1
+pinseq=3
+T 43500 47400 5 10 0 0 0 8 1
+pintype=pas
+}
+L 43550 46725 43550 46875 3 0 0 0 -1 -1
+L 43550 46925 43550 47075 3 0 0 0 -1 -1
+L 43550 47125 43550 47275 3 0 0 0 -1 -1
+L 43600 46800 43600 47200 3 0 0 0 -1 -1
+L 43550 47000 43400 47000 3 0 0 0 -1 -1
+L 43400 47000 43400 47200 3 0 0 0 -1 -1
+T 43200 46900 5 10 0 0 0 8 1
+device=PMOS_TRANSISTOR
+T 43200 46900 5 10 0 0 0 8 1
+numslots=0
+T 43200 46900 5 10 0 0 0 8 1
+description=generic P channel MOS transistor (enhancement type)
+T 43100 46800 8 10 0 1 0 8 1
+refdes=Q?
+]
+{
+T 43200 46900 5 10 0 0 0 8 1
+device=PMOS_TRANSISTOR
+T 43700 47000 5 10 1 1 180 8 1
+refdes=Q5
+T 43700 46800 5 10 1 1 0 0 1
+device=RFP30P05
+T 43700 46600 5 10 1 1 0 0 1
+footprint=TO220W
+}
+T 42300 43400 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
 

--- /dev/null
+++ b/schem/fp/SCREW125MIL.fp
@@ -1,1 +1,6 @@
+Element[0x0 "SCREW125MIL.fp" "" "" 200000 120000 70897 -10000 0 100 0x0]
+(
+   Pin[0 0 16500 12500 1250 12500 "" "1" 0x01]
+   ElementArc[0 0 10000 10000 0 360 1000]
+)
 

--- /dev/null
+++ b/schem/sym/NMOS.sym
@@ -1,1 +1,77 @@
+v 20130925 2
+L 250 600 500 600 3 0 0 0 -1 -1
+L 250 200 500 200 3 0 0 0 -1 -1
+L 250 400 350 450 3 0 0 0 -1 -1
+L 250 400 350 350 3 0 0 0 -1 -1
+P 0 200 200 200 1 0 0
+{
+T 105 245 5 10 0 1 0 6 1
+pinnumber=1
+T 255 195 9 10 0 1 0 0 1
+pinlabel=G
+T 0 300 5 10 0 0 0 0 1
+pinseq=1
+T 0 300 5 10 0 0 0 0 1
+pintype=pas
+T 0 200 5 10 0 0 0 0 1
+pintype=unknown
+T 255 195 5 10 0 1 0 0 1
+pinlabel=unknown
+T 105 245 5 10 0 1 0 6 1
+pinnumber=0
+T 0 200 5 10 0 0 0 0 1
+pinseq=0
+}
+P 500 600 500 800 1 0 1
+{
+T 450 695 5 10 0 1 90 0 1
+pinnumber=2
+T 500 545 9 10 0 1 90 6 1
+pinlabel=D
+T 300 700 5 10 0 0 0 0 1
+pinseq=2
+T 300 700 5 10 0 0 0 0 1
+pintype=pas
+T 500 600 5 10 0 0 0 0 1
+pintype=unknown
+T 500 545 5 10 0 1 90 6 1
+pinlabel=unknown
+T 450 695 5 10 0 1 90 0 1
+pinnumber=0
+T 500 600 5 10 0 0 0 0 1
+pinseq=0
+}
+P 500 200 500 0 1 0 1
+{
+T 450 105 5 10 0 1 90 6 1
+pinnumber=3
+T 500 255 9 10 0 1 90 0 1
+pinlabel=S
+T 300 0 5 10 0 0 0 0 1
+pinseq=3
+T 300 0 5 10 0 0 0 0 1
+pintype=pas
+T 500 200 5 10 0 0 0 0 1
+pintype=unknown
+T 500 255 5 10 0 1 90 0 1
+pinlabel=unknown
+T 450 105 5 10 0 1 90 6 1
+pinnumber=0
+T 500 200 5 10 0 0 0 0 1
+pinseq=0
+}
+L 250 675 250 525 3 0 0 0 -1 -1
+L 250 475 250 325 3 0 0 0 -1 -1
+L 250 275 250 125 3 0 0 0 -1 -1
+L 200 600 200 200 3 0 0 0 -1 -1
+L 250 400 400 400 3 0 0 0 -1 -1
+L 400 400 400 200 3 0 0 0 -1 -1
+T 600 500 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 600 500 5 10 0 0 0 0 1
+numslots=0
+T 600 500 5 10 0 0 0 0 1
+description=generic N channel MOS transistor (enhancement type)
+T 600 600 8 10 1 1 0 0 1
+refdes=Q?
 

file:b/schem/sym/NPN.sym (new)
--- /dev/null
+++ b/schem/sym/NPN.sym
@@ -1,1 +1,50 @@
+v 20110115 2
+P 600 1000 600 800 1 0 0
+{
+T 500 850 5 6 1 1 0 0 1
+pinnumber=3
+T 500 850 5 6 0 0 0 0 1
+pinseq=3
+T 500 850 5 6 0 1 0 0 1
+pinlabel=3
+T 500 850 5 6 0 1 0 0 1
+pintype=pas
+}
+P 600 200 600 0 1 0 1
+{
+T 500 50 5 6 1 1 0 0 1
+pinnumber=2
+T 500 50 5 6 0 0 0 0 1
+pinseq=2
+T 500 50 5 6 0 1 0 0 1
+pinlabel=2
+T 500 50 5 6 0 1 0 0 1
+pintype=pas
+}
+V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 600 200 400 400 3 0 0 0 -1 -1
+L 600 800 400 600 3 0 0 0 -1 -1
+L 400 700 400 300 3 0 0 0 -1 -1
+P 0 500 184 500 1 0 0
+{
+T 100 550 5 6 1 1 0 0 1
+pinnumber=1
+T 100 550 5 6 0 0 0 0 1
+pinseq=1
+T 100 550 5 6 0 1 0 0 1
+pinlabel=1
+T 100 550 5 6 0 1 0 0 1
+pintype=pas
+}
+L 400 500 184 500 3 0 0 0 -1 -1
+H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5
+M 510,240
+L 601,200
+L 555,295
+L 535,265
+z
+T 900 500 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 900 500 8 10 1 1 0 0 1
+refdes=Q?
 

--- /dev/null
+++ b/schem/sym/PMOS.sym
@@ -1,1 +1,53 @@
+v 20130925 2
+L 250 600 500 600 3 0 0 0 -1 -1
+L 250 200 500 200 3 0 0 0 -1 -1
+L 300 350 400 400 3 0 0 0 -1 -1
+L 300 450 400 400 3 0 0 0 -1 -1
+P 0 200 200 200 1 0 0
+{
+T 0 300 5 10 0 1 0 0 1
+pinnumber=1
+T 0 300 9 10 0 1 0 0 1
+pinlabel=1
+T 0 300 5 10 0 0 0 0 1
+pinseq=1
+T 0 300 5 10 0 0 0 0 1
+pintype=pas
+}
+P 500 600 500 800 1 0 1
+{
+T 300 700 5 10 0 1 0 0 1
+pinnumber=2
+T 300 700 9 10 0 1 0 0 1
+pinlabel=2
+T 300 700 5 10 0 0 0 0 1
+pinseq=2
+T 300 700 5 10 0 0 0 0 1
+pintype=pas
+}
+P 500 200 500 0 1 0 1
+{
+T 300 0 5 10 0 1 0 0 1
+pinnumber=3
+T 300 0 9 10 0 1 0 0 1
+pinlabel=3
+T 300 0 5 10 0 0 0 0 1
+pinseq=3
+T 300 0 5 10 0 0 0 0 1
+pintype=pas
+}
+L 250 675 250 525 3 0 0 0 -1 -1
+L 250 475 250 325 3 0 0 0 -1 -1
+L 250 275 250 125 3 0 0 0 -1 -1
+L 200 600 200 200 3 0 0 0 -1 -1
+L 250 400 400 400 3 0 0 0 -1 -1
+L 400 400 400 200 3 0 0 0 -1 -1
+T 600 500 5 10 0 0 0 0 1
+device=PMOS_TRANSISTOR
+T 600 500 5 10 0 0 0 0 1
+numslots=0
+T 600 500 5 10 0 0 0 0 1
+description=generic P channel MOS transistor (enhancement type)
+T 700 600 8 10 1 1 0 0 1
+refdes=Q?