Created PA0RDT MiniWhip Repository master
Created PA0RDT MiniWhip Repository

--- /dev/null
+++ b/MiniWhip/PA0RDT.net
@@ -1,1 +1,10 @@
+unnamed_net8	SIGOUT-1 C2-2 L1-1 
+unnamed_net7	C2-1 Q2-2 R8-2 
+unnamed_net6	Q2-1 R7-2 
+unnamed_net5	R7-1 C1-2 R6-2 R5-1 
+unnamed_net4	C1-1 Q1-3 R4-2 
+GND	C4-1 C3-1 SIGOUT-2 R4-1 R6-1 R8-1 R3-1 
+unnamed_net3	U?-? Q1-1 R2-2 
+unnamed_net2	R3-2 R2-1 R1-1 
+unnamed_net1	Q2-3 R5-2 Q1-2 C3-2 C4-2 L1-2 R1-2 
 

--- /dev/null
+++ b/MiniWhip/PA0RDT.pcb
@@ -1,1 +1,1402 @@
-
+# release: pcb 20110918
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
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+	Line[243649 70026 244436 70026 1000 2000 "clearline"]
+	Line[242862 70813 243649 70026 1000 2000 "clearline"]
+	Line[238137 70813 242862 70813 1000 2000 "clearline"]
+	Line[237350 70026 238137 70813 1000 2000 "clearline"]
+	Line[236562 70026 237350 70026 1000 2000 "clearline"]
+	Line[235774 69238 236562 70026 1000 2000 "clearline"]
+	Line[234987 69238 235774 69238 1000 2000 "clearline"]
+	Line[234987 68451 234200 67664 1000 2000 "clearline"]
+	Line[234200 69238 234987 68451 1000 2000 "clearline"]
+	Line[234200 70813 234200 69238 1000 2000 "clearline"]
+	Line[234987 71600 234200 70813 1000 2000 "clearline"]
+	Line[234987 73176 234987 71600 1000 2000 "clearline"]
+	Line[234200 73963 234987 73176 1000 2000 "clearline"]
+	Line[234200 76325 234200 73963 1000 2000 "clearline"]
+	Line[232625 70026 232625 69238 1000 2000 "clearline"]
+	Line[231838 70813 232625 70026 1000 2000 "clearline"]
+	Line[231838 73176 231838 70813 1000 2000 "clearline"]
+	Line[231050 73964 231838 73176 1000 2000 "clearline"]
+	Line[231050 76325 231050 73964 1000 2000 "clearline"]
+	Line[221602 72389 224751 75538 1000 2000 "clearline"]
+	Line[221602 72388 221602 72389 1000 2000 "clearline"]
+	Line[223176 59001 221602 57427 1000 2000 "clearline"]
+	Line[223176 59790 223176 59001 1000 2000 "clearline"]
+	Line[225538 62152 223176 59790 1000 2000 "clearline"]
+	Line[225539 62152 225538 62152 1000 2000 "clearline"]
+	Line[227901 64514 225539 62152 1000 2000 "clearline"]
+	Line[227901 65301 227901 64514 1000 2000 "clearline"]
+	Line[229476 66876 227901 65301 1000 2000 "clearline"]
+	Line[230263 66876 229476 66876 1000 2000 "clearline"]
+	Line[231051 67664 230263 66876 1000 2000 "clearline"]
+	Line[232625 67664 231051 67664 1000 2000 "clearline"]
+	Line[233413 66876 231838 68451 1000 2000 "clearline"]
+	Line[232625 68451 231838 69238 1000 2000 "clearline"]
+	Line[232625 67664 232625 68451 1000 2000 "clearline"]
+	Line[231838 69238 231838 68451 1000 2000 "clearline"]
+	Line[234200 66876 233413 66876 1000 2000 "clearline"]
+	Line[232625 65301 234200 66876 1000 2000 "clearline"]
+	Line[232625 64514 232625 65301 1000 2000 "clearline"]
+	Line[231838 63727 232625 64514 1000 2000 "clearline"]
+	Line[232626 62939 231838 63727 1000 2000 "clearline"]
+	Line[233413 62939 232626 62939 1000 2000 "clearline"]
+	Line[233413 60577 233413 62939 1000 2000 "clearline"]
+	Line[232626 59790 233413 60577 1000 2000 "clearline"]
+	Line[231838 59790 232626 59790 1000 2000 "clearline"]
+	Line[231050 59002 231838 59790 1000 2000 "clearline"]
+	Line[230263 59002 231050 59002 1000 2000 "clearline"]
+	Line[229476 58215 230263 59002 1000 2000 "clearline"]
+	Line[229476 57427 229476 58215 1000 2000 "clearline"]
+	Line[228689 56640 229476 57427 1000 2000 "clearline"]
+	Line[227901 56640 228689 56640 1000 2000 "clearline"]
+	Line[227114 55853 227901 56640 1000 2000 "clearline"]
+	Line[226326 55853 227114 55853 1000 2000 "clearline"]
+	Line[225539 55066 226326 55853 1000 2000 "clearline"]
+	Line[225539 54278 225539 55066 1000 2000 "clearline"]
+	Line[226326 53491 225539 54278 1000 2000 "clearline"]
+	Line[226326 53490 226326 53491 1000 2000 "clearline"]
+	Line[227901 53490 226326 53490 1000 2000 "clearline"]
+	Line[228689 54278 227901 53490 1000 2000 "clearline"]
+	Line[231050 54278 228689 54278 1000 2000 "clearline"]
+	Line[231838 53490 231050 54278 1000 2000 "clearline"]
+	Line[231838 51916 231838 53490 1000 2000 "clearline"]
+	Line[234200 49554 231838 51916 1000 2000 "clearline"]
+	Line[234200 47979 234200 49554 1000 2000 "clearline"]
+	Line[236563 45616 234200 47979 1000 2000 "clearline"]
+	Line[238137 45616 236563 45616 1000 2000 "clearline"]
+	Line[239712 48766 239712 47191 1000 2000 "clearline"]
+	Line[239712 46404 238925 46404 1000 2000 "clearline"]
+	Line[240500 45616 239712 46404 1000 2000 "clearline"]
+	Line[242074 45616 240500 45616 1000 2000 "clearline"]
+	Line[242861 46403 242074 45616 1000 2000 "clearline"]
+	Line[242861 46404 242861 46403 1000 2000 "clearline"]
+	Line[243649 45616 242861 46404 1000 2000 "clearline"]
+	Line[245224 45616 243649 45616 1000 2000 "clearline"]
+	Line[246011 46403 245224 45616 1000 2000 "clearline"]
+	Line[246011 46404 246011 46403 1000 2000 "clearline"]
+	Line[246798 47191 246011 46404 1000 2000 "clearline"]
+	Line[247586 47191 246798 47191 1000 2000 "clearline"]
+	Line[246799 46404 247586 47191 1000 2000 "clearline"]
+	Line[246798 46404 246799 46404 1000 2000 "clearline"]
+	Line[247586 45616 246798 46404 1000 2000 "clearline"]
+	Line[248373 45616 247586 45616 1000 2000 "clearline"]
+	Line[249161 46404 248373 45616 1000 2000 "clearline"]
+	Line[249948 46404 249161 46404 1000 2000 "clearline"]
+	Line[250735 47191 249948 46404 1000 2000 "clearline"]
+	Line[251523 47191 250735 47191 1000 2000 "clearline"]
+	Line[253098 48766 251523 47191 1000 2000 "clearline"]
+	Line[252311 47979 253098 48766 1000 2000 "clearline"]
+	Line[252310 47979 252311 47979 1000 2000 "clearline"]
+	Line[253098 47191 252310 47979 1000 2000 "clearline"]
+	Line[254672 47191 253098 47191 1000 2000 "clearline"]
+	Line[255460 47979 254672 47191 1000 2000 "clearline"]
+	Line[256247 47979 255460 47979 1000 2000 "clearline"]
+	Line[257034 48766 256247 47979 1000 2000 "clearline"]
+	Line[257035 48766 257034 48766 1000 2000 "clearline"]
+	Line[257822 49553 257035 48766 1000 2000 "clearline"]
+	Line[258609 49553 257822 49553 1000 2000 "clearline"]
+	Line[259397 50341 258609 49553 1000 2000 "clearline"]
+	Line[259397 51128 259397 50341 1000 2000 "clearline"]
+	Line[260184 51915 259397 51128 1000 2000 "clearline"]
+	Line[260184 52703 260184 51915 1000 2000 "clearline"]
+	Line[259397 53490 260184 52703 1000 2000 "clearline"]
+	Line[259397 54278 259397 53490 1000 2000 "clearline"]
+	Line[258610 55065 259397 54278 1000 2000 "clearline"]
+	Line[258609 55065 258610 55065 1000 2000 "clearline"]
+	Line[257822 55852 258609 55065 1000 2000 "clearline"]
+	Line[257822 55853 257822 55852 1000 2000 "clearline"]
+	Line[257035 56640 257822 55853 1000 2000 "clearline"]
+	Line[257035 57427 257035 56640 1000 2000 "clearline"]
+	Line[256247 57427 257035 57427 1000 2000 "clearline"]
+	Line[255459 58215 256247 57427 1000 2000 "clearline"]
+	Line[254672 58215 255459 58215 1000 2000 "clearline"]
+	Line[253097 59790 254672 58215 1000 2000 "clearline"]
+	Line[252310 59790 253097 59790 1000 2000 "clearline"]
+	Line[251523 60577 252310 59790 1000 2000 "clearline"]
+	Line[254672 75538 260184 70026 1000 2000 "clearline"]
+	Text[218400 79200 0 100 "I can wire anything directly" "clearline"]
+	Text[218100 86500 0 100 "into anything I'm the Professor!" "clearline"]
+	Text[183200 106600 0 100 "DrYerzinia" "clearline"]
+	Text[296000 108100 0 100 "PA0RDT Mini-Whip r2" "clearline"]
+)
+NetList()
+(
+	Net("GND" "(unknown)")
+	(
+		Connect("C3-1")
+		Connect("C4-1")
+		Connect("R3-1")
+		Connect("R4-1")
+		Connect("R6-1")
+		Connect("R8-1")
+		Connect("SIGOUT-2")
+	)
+	Net("unnamed_net1" "(unknown)")
+	(
+		Connect("C3-2")
+		Connect("C4-2")
+		Connect("L1-2")
+		Connect("Q1-2")
+		Connect("Q2-3")
+		Connect("R1-2")
+		Connect("R5-2")
+	)
+	Net("unnamed_net2" "(unknown)")
+	(
+		Connect("R1-1")
+		Connect("R2-1")
+		Connect("R3-2")
+	)
+	Net("unnamed_net3" "(unknown)")
+	(
+		Connect("Q1-1")
+		Connect("R2-2")
+		Connect("U?-?")
+	)
+	Net("unnamed_net4" "(unknown)")
+	(
+		Connect("C1-1")
+		Connect("Q1-3")
+		Connect("R4-2")
+	)
+	Net("unnamed_net5" "(unknown)")
+	(
+		Connect("C1-2")
+		Connect("R5-1")
+		Connect("R6-2")
+		Connect("R7-1")
+	)
+	Net("unnamed_net6" "(unknown)")
+	(
+		Connect("Q2-1")
+		Connect("R7-2")
+	)
+	Net("unnamed_net7" "(unknown)")
+	(
+		Connect("C2-1")
+		Connect("Q2-2")
+		Connect("R8-2")
+	)
+	Net("unnamed_net8" "(unknown)")
+	(
+		Connect("C2-2")
+		Connect("L1-1")
+		Connect("SIGOUT-1")
+	)
+)
+

--- /dev/null
+++ b/MiniWhip/PA0RDT.sch
@@ -1,1 +1,223 @@
+v 20130925 2
+C 42500 46900 1 90 0 resistor-1.sym
+{
+T 42100 47200 5 10 0 0 90 0 1
+device=RESISTOR
+T 41800 47500 5 10 1 1 0 0 1
+refdes=R1
+T 41800 47300 5 10 1 1 0 0 1
+footprint=0805
+T 41800 47100 5 10 1 1 0 0 1
+value=1M
+}
+C 43500 44900 1 90 0 resistor-1.sym
+{
+T 43100 45200 5 10 0 0 90 0 1
+device=RESISTOR
+T 42800 45500 5 10 1 1 0 0 1
+refdes=R2
+T 42800 45300 5 10 1 1 0 0 1
+footprint=0805
+T 42800 45100 5 10 1 1 0 0 1
+value=1M
+}
+C 43500 43400 1 90 0 resistor-1.sym
+{
+T 43100 43700 5 10 0 0 90 0 1
+device=RESISTOR
+T 42800 44000 5 10 1 1 0 0 1
+refdes=R3
+T 42800 43800 5 10 1 1 0 0 1
+footprint=0805
+T 42800 43600 5 10 1 1 0 0 1
+value=1M
+}
+C 44300 43400 1 90 0 resistor-1.sym
+{
+T 43900 43700 5 10 0 0 90 0 1
+device=RESISTOR
+T 43600 44000 5 10 1 1 0 0 1
+refdes=R4
+T 43600 43800 5 10 1 1 0 0 1
+footprint=0805
+T 43600 43600 5 10 1 1 0 0 1
+value=680
+}
+C 46100 46700 1 90 0 resistor-1.sym
+{
+T 45700 47000 5 10 0 0 90 0 1
+device=RESISTOR
+T 45400 47300 5 10 1 1 0 0 1
+refdes=R5
+T 45400 47100 5 10 1 1 0 0 1
+footprint=0805
+T 45400 46900 5 10 1 1 0 0 1
+value=2K2
+}
+C 46100 43400 1 90 0 resistor-1.sym
+{
+T 45700 43700 5 10 0 0 90 0 1
+device=RESISTOR
+T 45400 44000 5 10 1 1 0 0 1
+refdes=R6
+T 45400 43800 5 10 1 1 0 0 1
+footprint=0805
+T 45400 43600 5 10 1 1 0 0 1
+value=10K
+}
+C 46500 44900 1 0 0 resistor-1.sym
+{
+T 46800 45300 5 10 0 0 0 0 1
+device=RESISTOR
+T 46400 45100 5 10 1 1 0 0 1
+refdes=R7
+T 46700 45200 5 10 1 1 0 0 1
+footprint=0805
+T 47200 45100 5 10 1 1 0 0 1
+value=47
+}
+C 48300 43400 1 90 0 resistor-1.sym
+{
+T 47900 43700 5 10 0 0 90 0 1
+device=RESISTOR
+T 47600 44000 5 10 1 1 0 0 1
+refdes=R8
+T 47600 43800 5 10 1 1 0 0 1
+footprint=0805
+T 47600 43600 5 10 1 1 0 0 1
+value=220
+}
+N 42400 46900 42400 44700 4
+N 42400 44700 43400 44700 4
+N 43400 44300 43400 44900 4
+C 43600 45600 1 0 0 NJFET.sym
+{
+T 44500 46100 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 44500 46300 5 10 1 1 0 0 1
+refdes=Q1
+T 44500 46100 5 10 1 1 0 0 1
+footprint=SOT23
+T 44500 45900 5 10 1 1 0 0 1
+device=J310
+}
+N 41500 46000 43600 46000 4
+N 43400 46000 43400 45800 4
+N 44200 44300 44200 45600 4
+C 44400 44800 1 0 0 capacitor-1.sym
+{
+T 44600 45500 5 10 0 0 0 0 1
+device=CAPACITOR
+T 44400 45100 5 10 1 1 0 0 1
+refdes=C1
+T 44600 45700 5 10 0 0 0 0 1
+symversion=0.1
+T 45000 44800 5 10 1 1 0 0 1
+footprint=0805
+T 45000 45100 5 10 1 1 0 0 1
+value=100nF
+}
+N 44400 45000 44200 45000 4
+N 46000 44300 46000 46700 4
+N 46000 45000 45300 45000 4
+N 46500 45000 46000 45000 4
+C 47600 44500 1 0 0 NPN.sym
+{
+T 48500 45000 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 48500 45200 5 10 1 1 0 0 1
+refdes=Q2
+T 48500 44800 5 10 1 1 0 0 1
+footprint=SOT23D
+T 48500 45000 5 10 1 1 0 0 1
+device=H6327
+}
+N 47400 45000 47600 45000 4
+N 48200 44300 48200 44500 4
+C 50100 45500 1 90 0 inductor-dot-1.sym
+{
+T 49700 45700 5 10 0 0 90 0 1
+device=INDUCTOR
+T 49200 46100 5 10 1 1 0 0 1
+refdes=L1
+T 49500 45700 5 10 0 0 90 0 1
+symversion=0.1
+T 49200 45700 5 10 1 1 0 0 1
+value=470uH
+T 49200 45900 5 10 1 1 0 0 1
+footprint=SRR7032
+}
+C 48600 44200 1 0 0 capacitor-1.sym
+{
+T 48800 44900 5 10 0 0 0 0 1
+device=CAPACITOR
+T 48600 44500 5 10 1 1 0 0 1
+refdes=C2
+T 48800 45100 5 10 0 0 0 0 1
+symversion=0.1
+T 49200 44200 5 10 1 1 0 0 1
+footprint=0805
+T 49200 44500 5 10 1 1 0 0 1
+value=100nF
+}
+N 48600 44400 48200 44400 4
+N 49500 44400 51000 44400 4
+N 50100 44400 50100 45500 4
+C 43400 46900 1 90 0 capacitor-1.sym
+{
+T 42700 47100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 42800 47500 5 10 1 1 0 0 1
+refdes=C3
+T 42500 47100 5 10 0 0 90 0 1
+symversion=0.1
+T 43300 47500 5 10 1 1 0 0 1
+footprint=0805
+T 43300 47100 5 10 1 1 0 0 1
+value=100nF
+}
+C 49100 46900 1 90 0 capacitor-1.sym
+{
+T 48400 47100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 48500 47500 5 10 1 1 0 0 1
+refdes=C4
+T 48200 47100 5 10 0 0 90 0 1
+symversion=0.1
+T 49000 47500 5 10 1 1 0 0 1
+footprint=0805
+T 49000 47100 5 10 1 1 0 0 1
+value=100nF
+}
+N 50100 46400 50100 48000 4
+N 42400 48000 50100 48000 4
+N 48900 48000 48900 47800 4
+N 42400 48000 42400 47800 4
+N 43200 47800 43200 48000 4
+C 43300 42700 1 0 0 gnd-1.sym
+C 48800 46400 1 0 0 gnd-1.sym
+C 43100 46400 1 0 0 gnd-1.sym
+N 43200 46700 43200 46900 4
+N 48900 46700 48900 46900 4
+N 43400 43000 43400 43400 4
+N 43400 43200 51400 43200 4
+N 48200 43200 48200 43400 4
+N 46000 43400 46000 43200 4
+N 44200 43400 44200 43200 4
+N 44200 46600 44200 48000 4
+N 46000 47600 46000 48000 4
+N 48200 45500 48200 48000 4
+C 51500 43900 1 0 1 BNC-1.sym
+{
+T 51600 44500 5 10 1 1 0 0 1
+refdes=SIGOUT
+T 51600 44200 5 10 1 1 0 0 1
+footprint=BNC_LAY
+}
+N 51400 43200 51400 43900 4
+C 40900 45800 1 0 0 output.sym
+{
+T 40900 46300 5 10 1 1 0 0 1
+device=Probe
+}
 

--- /dev/null
+++ b/MiniWhip/fp/SRR7032.fp
@@ -1,1 +1,12 @@
+Element[0x00000000 "Coil" "" "SRR7032" 0 0 -101 -101 0 100 ""]
+(
+	Pad[-11811 1181 -11811 -1181 7087 2000 5718 "1" "1" "square"]
+	Pad[11811 1181 11811 -1181 7087 2000 5718 "2" "2" "square"]
 
+	ElementLine[-13780 13780 13780 13780 1000]
+	ElementLine[-13780 -13780 13780 -13780 1000]
+
+)
+
+
+

--- /dev/null
+++ b/MiniWhip/sym/NJFET.sym
@@ -1,1 +1,63 @@
+v 20130925 2
+P 600 1000 600 800 1 0 0
+{
+T 500 850 5 6 0 0 0 0 1
+pinseq=1
+T 600 745 5 6 0 1 90 6 1
+pinlabel=D
+T 500 850 5 6 0 1 0 0 1
+pintype=pas
+T 600 1000 5 10 0 0 0 0 1
+pintype=unknown
+T 395 850 5 10 1 1 0 0 1
+pinnumber=2
+T 600 1000 5 10 0 0 0 0 1
+pinseq=0
+}
+P 600 200 600 0 1 0 1
+{
+T 500 50 5 6 0 0 0 0 1
+pinseq=3
+T 600 255 5 6 0 1 90 0 1
+pinlabel=S
+T 500 50 5 6 0 1 0 0 1
+pintype=pas
+T 600 200 5 10 0 0 0 0 1
+pintype=unknown
+T 395 50 5 10 1 1 0 0 1
+pinnumber=3
+T 600 200 5 10 0 0 0 0 1
+pinseq=0
+}
+V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 400 700 400 300 3 0 0 0 -1 -1
+P 0 400 184 400 1 0 0
+{
+T 100 450 5 6 0 0 0 0 1
+pinseq=2
+T 239 395 5 6 0 1 0 0 1
+pinlabel=G
+T 100 450 5 6 0 1 0 0 1
+pintype=pas
+T 0 400 5 10 0 0 0 0 1
+pintype=unknown
+T 11 445 5 10 1 1 0 0 1
+pinnumber=1
+T 0 400 5 10 0 0 0 0 1
+pinseq=0
+}
+L 400 400 184 400 3 0 0 0 -1 -1
+L 600 800 600 600 3 0 0 0 -1 -1
+L 400 600 600 600 3 0 0 0 -1 -1
+L 400 400 600 400 3 0 0 0 -1 -1
+L 600 200 600 400 3 0 0 0 -1 -1
+L 400 400 360 380 3 0 0 0 -1 -1
+L 360 380 360 420 3 0 0 0 -1 -1
+L 360 420 400 400 3 0 0 0 -1 -1
+T 900 500 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 900 500 8 10 1 1 0 0 1
+refdes=Q?
+T 900 300 8 10 1 1 0 0 1
+footprint=SOT23D
 

--- /dev/null
+++ b/MiniWhip/sym/NPN.sym
@@ -1,1 +1,50 @@
+v 20110115 2
+P 600 1000 600 800 1 0 0
+{
+T 500 850 5 6 1 1 0 0 1
+pinnumber=3
+T 500 850 5 6 0 0 0 0 1
+pinseq=3
+T 500 850 5 6 0 1 0 0 1
+pinlabel=3
+T 500 850 5 6 0 1 0 0 1
+pintype=pas
+}
+P 600 200 600 0 1 0 1
+{
+T 500 50 5 6 1 1 0 0 1
+pinnumber=2
+T 500 50 5 6 0 0 0 0 1
+pinseq=2
+T 500 50 5 6 0 1 0 0 1
+pinlabel=2
+T 500 50 5 6 0 1 0 0 1
+pintype=pas
+}
+V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 600 200 400 400 3 0 0 0 -1 -1
+L 600 800 400 600 3 0 0 0 -1 -1
+L 400 700 400 300 3 0 0 0 -1 -1
+P 0 500 184 500 1 0 0
+{
+T 100 550 5 6 1 1 0 0 1
+pinnumber=1
+T 100 550 5 6 0 0 0 0 1
+pinseq=1
+T 100 550 5 6 0 1 0 0 1
+pinlabel=1
+T 100 550 5 6 0 1 0 0 1
+pintype=pas
+}
+L 400 500 184 500 3 0 0 0 -1 -1
+H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5
+M 510,240
+L 601,200
+L 555,295
+L 535,265
+z
+T 900 500 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 900 500 8 10 1 1 0 0 1
+refdes=Q?
 

--- /dev/null
+++ b/PowerInjector/PowerInjector.net
@@ -1,1 +1,7 @@
+unnamed_net5	F1-2 D1-2 
+unnamed_net4	PWR-1 D1-1 C3-2 
+unnamed_net3	C1-2 SIGOUT-1 
+GND	PWR-2 C3-1 SIGIN-2 C2-1 SIGOUT-2 
+unnamed_net2	SIGIN-1 C1-1 L1-1 
+unnamed_net1	C2-2 F1-1 L1-2 
 

--- /dev/null
+++ b/PowerInjector/PowerInjector.pcb
@@ -1,1 +1,1245 @@
-
+# release: pcb 20110918
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20070407]
+
+PCB["" 125000 104000]
+
+Grid[500.0 0 0 0]
+Cursor[63500 93500 0.000000]
+PolyArea[200000000.000000]
+Thermal[0.500000]
+DRC[1000 1000 1000 1000 1500 1000]
+Flags("nameonpcb,uniquename,clearnew,snappin")
+Groups("1,c:2:3:4:5:6,s:7:8")
+Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
+
+Symbol[' ' 1800]
+(
+)
+Symbol['!' 1200]
+(
+	SymbolLine[0 4500 0 5000 800]
+	SymbolLine[0 1000 0 3500 800]
+)
+Symbol['"' 1200]
+(
+	SymbolLine[0 1000 0 2000 800]
+	SymbolLine[1000 1000 1000 2000 800]
+)
+Symbol['#' 1200]
+(
+	SymbolLine[0 3500 2000 3500 800]
+	SymbolLine[0 2500 2000 2500 800]
+	SymbolLine[1500 2000 1500 4000 800]
+	SymbolLine[500 2000 500 4000 800]
+)
+Symbol['$' 1200]
+(
+	SymbolLine[1500 1500 2000 2000 800]
+	SymbolLine[500 1500 1500 1500 800]
+	SymbolLine[0 2000 500 1500 800]
+	SymbolLine[0 2000 0 2500 800]
+	SymbolLine[0 2500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 2000 4000 800]
+	SymbolLine[1500 4500 2000 4000 800]
+	SymbolLine[500 4500 1500 4500 800]
+	SymbolLine[0 4000 500 4500 800]
+	SymbolLine[1000 1000 1000 5000 800]
+)
+Symbol['%' 1200]
+(
+	SymbolLine[0 1500 0 2000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1000 1000 800]
+	SymbolLine[1000 1000 1500 1500 800]
+	SymbolLine[1500 1500 1500 2000 800]
+	SymbolLine[1000 2500 1500 2000 800]
+	SymbolLine[500 2500 1000 2500 800]
+	SymbolLine[0 2000 500 2500 800]
+	SymbolLine[0 5000 4000 1000 800]
+	SymbolLine[3500 5000 4000 4500 800]
+	SymbolLine[4000 4000 4000 4500 800]
+	SymbolLine[3500 3500 4000 4000 800]
+	SymbolLine[3000 3500 3500 3500 800]
+	SymbolLine[2500 4000 3000 3500 800]
+	SymbolLine[2500 4000 2500 4500 800]
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+	ElementLine [-2755 -393 -2755 393 800]
+
+	)
+
+Element["onsolder" "BNC_LAY" "SIGIN" "unknown" 31500 51500 27500 7000 2 100 "auto"]
+(
+	Pin[0 0 6000 3000 6600 3500 "1" "1" "square,edge2"]
+	Pin[10000 0 6000 3000 6600 3500 "2" "2" "edge2"]
+	Pin[20000 -20000 10000 3000 10600 8100 "m1" "3" "edge2"]
+	Pin[-20000 -20000 10000 3000 10600 8100 "m2" "4" "edge2"]
+	ElementLine [29000 -49000 29000 6000 1000]
+	ElementLine [-29000 -49000 29000 -49000 1000]
+	ElementLine [-29000 -49000 -29000 6000 1000]
+	ElementLine [-29000 6000 29000 6000 1000]
+
+	)
+
+Element["" "0805" "C1" "100nF" 62457 52500 -2650 -9650 0 100 ""]
+(
+	Pad[-3543 -393 -3543 393 5118 2000 5718 "1" "1" "square"]
+	Pad[3543 -393 3543 393 5118 2000 5718 "2" "2" "square"]
+	ElementLine [-393 -2755 393 -2755 800]
+	ElementLine [-393 2755 393 2755 800]
+
+	)
+
+Element["" "0805" "C2" "100nF" 96543 70000 -4650 -9650 0 100 ""]
+(
+	Pad[3543 -393 3543 393 5118 2000 5718 "1" "1" "square"]
+	Pad[-3543 -393 -3543 393 5118 2000 5718 "2" "2" "square"]
+	ElementLine [-393 2755 393 2755 800]
+	ElementLine [-393 -2755 393 -2755 800]
+
+	)
+
+Element["" "SRR7032" "L1" "470uH" 70689 71500 -27101 -3601 0 100 ""]
+(
+	Pad[-11811 -1181 -11811 1181 7087 2000 5718 "1" "1" "square"]
+	Pad[11811 -1181 11811 1181 7087 2000 5718 "2" "2" "selected,square"]
+	ElementLine [-13780 13780 13780 13780 1000]
+	ElementLine [-13780 -13780 13780 -13780 1000]
+
+	)
+
+Element["onsolder" "BNC_LAY" "SIGOUT" "unknown" 92500 51500 -10500 6500 2 100 "auto"]
+(
+	Pin[0 0 6000 3000 6600 3500 "1" "1" "square,edge2"]
+	Pin[10000 0 6000 3000 6600 3500 "2" "2" "edge2"]
+	Pin[20000 -20000 10000 3000 10600 8100 "m1" "3" "edge2"]
+	Pin[-20000 -20000 10000 3000 10600 8100 "m2" "4" "edge2"]
+	ElementLine [29000 -49000 29000 6000 1000]
+	ElementLine [-29000 -49000 29000 -49000 1000]
+	ElementLine [-29000 -49000 -29000 6000 1000]
+	ElementLine [-29000 6000 29000 6000 1000]
+
+	)
+Layer(1 "top")
+(
+	Line[21500 82414 11914 82414 1000 2000 "clearline"]
+	Line[11914 82414 11000 81500 1000 2000 "clearline"]
+	Line[13000 89500 11000 91500 1000 2000 "clearline"]
+	Line[13000 89500 30500 89500 1000 2000 "clearline"]
+	Line[30500 89500 31000 90000 1000 2000 "clearline"]
+	Line[48244 90000 60500 90000 1000 2000 "clearline"]
+	Line[80500 90000 80500 73500 1000 2000 "clearline"]
+	Line[58878 71500 58878 52536 1000 2000 "clearline"]
+	Line[58878 52536 58914 52500 1000 2000 "clearline"]
+	Line[93000 70000 84000 70000 1000 2000 "clearline"]
+	Line[80500 73500 84000 70000 1000 2000 "clearline"]
+	Line[102500 51500 102500 67586 1000 2000 "clearline"]
+	Line[102500 67586 100086 70000 1000 2000 "clearline"]
+	Line[21500 82414 21500 76000 1000 2000 "clearline"]
+	Line[21500 76000 30000 67500 1000 2000 "clearline"]
+	Line[30000 67500 37000 67500 1000 2000 "clearline"]
+	Line[37000 67500 41000 63500 1000 2000 "clearline"]
+	Line[41000 63500 41000 52000 1000 2000 "clearline"]
+	Line[41000 52000 41500 51500 1000 2000 "clearline"]
+	Line[66000 52500 91500 52500 1000 2000 "clearline"]
+	Line[91500 52500 92500 51500 1000 2000 "clearline"]
+	Line[31500 51500 31500 48000 1000 2000 "clearline"]
+	Line[31500 48000 33500 46000 1000 2000 "clearline"]
+	Line[33500 46000 57500 46000 1000 2000 "clearline"]
+	Line[57500 46000 58500 47000 1000 2000 "clearline"]
+	Line[58500 47000 58500 52086 1000 2000 "clearline"]
+	Line[58500 52086 58914 52500 1000 2000 "clearline"]
+	Line[102500 52000 102500 31500 1000 2000 "clearline"]
+	Line[112500 31500 51500 31500 1000 2000 "clearline"]
+	Line[51500 31500 52500 31500 1000 2000 "clearline"]
+	Line[52500 31500 11500 31500 1000 2000 "clearline"]
+	Line[21500 81000 21500 41500 1000 2000 "clearline"]
+	Line[21500 41500 11500 31500 1000 2000 "clearline"]
+	Polygon("")
+	(
+		[3000 3000] [121000 3000] [121000 99500] [3000 99500] [3000 96500] 
+		[54500 96500] [56500 94500] [88500 94500] [88500 75000] [109500 75000] 
+		[109500 45000] [67000 45000] [64500 42500] [26000 42500] [26000 57500] 
+		[50000 57500] [50000 80000] [26500 80000] [26500 75500] [6500 75500] 
+		[6500 85000] [4500 87000] [4500 96500] [3000 96500] 
+	)
+)
+Layer(2 "ground")
+(
+)
+Layer(3 "signal2")
+(
+)
+Layer(4 "signal3")
+(
+)
+Layer(5 "power")
+(
+)
+Layer(6 "bottom")
+(
+)
+Layer(7 "outline")
+(
+	Line[2500 2500 121500 2500 1000 2000 "clearline"]
+	Line[121500 2500 121500 100000 1000 2000 "clearline"]
+	Line[121500 100000 2500 100000 1000 2000 "clearline"]
+	Line[2500 100000 2500 2500 1000 2000 "clearline"]
+)
+Layer(8 "spare")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+	Line[112184 37026 112971 37026 1000 2000 "clearline"]
+	Line[101948 34664 101948 41751 1000 2000 "clearline"]
+	Line[106673 21278 107460 22065 1000 2000 "clearline"]
+	Line[106672 21278 106673 21278 1000 2000 "clearline"]
+	Line[106520 21430 106672 21278 1000 2000 "clearline"]
+	Line[106520 22312 106520 21430 1000 2000 "clearline"]
+	Line[108247 20490 108247 18916 1000 2000 "clearline"]
+	Line[104310 18128 104310 19703 1000 2000 "clearline"]
+	Line[103523 18128 104310 18128 1000 2000 "clearline"]
+	Line[101948 20491 101161 21278 1000 2000 "clearline"]
+	Line[101948 19703 101948 20491 1000 2000 "clearline"]
+	Line[101161 18916 101948 19703 1000 2000 "clearline"]
+	Line[101161 18128 101161 18916 1000 2000 "clearline"]
+	Line[109035 20490 108247 20490 1000 2000 "clearline"]
+	Line[109035 18916 109035 20490 1000 2000 "clearline"]
+	Line[108247 18128 109035 18916 1000 2000 "clearline"]
+	Line[107460 18915 108247 18128 1000 2000 "clearline"]
+	Line[107460 19703 107460 18915 1000 2000 "clearline"]
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+	Line[113759 25215 113759 24428 1000 2000 "clearline"]
+	Line[106673 32301 113759 25215 1000 2000 "clearline"]
+	Line[106672 32301 106673 32301 1000 2000 "clearline"]
+	Line[105097 33876 106672 32301 1000 2000 "clearline"]
+	Line[103523 33876 105097 33876 1000 2000 "clearline"]
+	Line[102736 33089 103523 33876 1000 2000 "clearline"]
+	Line[101948 33089 102736 33089 1000 2000 "clearline"]
+	Line[101160 32301 101948 33089 1000 2000 "clearline"]
+	Line[100373 32301 101160 32301 1000 2000 "clearline"]
+	Line[101948 41751 101161 42538 1000 2000 "clearline"]
+	Line[112971 37026 116121 33876 1000 2000 "clearline"]
+	Line[101161 33877 101948 34664 1000 2000 "clearline"]
+	Line[101161 33876 101161 33877 1000 2000 "clearline"]
+	Line[99586 32301 101161 33876 1000 2000 "clearline"]
+	Line[100373 29152 100373 28364 1000 2000 "clearline"]
+	Line[99586 29939 100373 29152 1000 2000 "clearline"]
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+	Line[99586 31514 98798 31514 1000 2000 "clearline"]
+	Line[101161 29939 99586 31514 1000 2000 "clearline"]
+	Line[101948 29939 101161 29939 1000 2000 "clearline"]
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+	Line[101161 26790 101948 27577 1000 2000 "clearline"]
+	Line[99586 26790 101161 26790 1000 2000 "clearline"]
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+	Line[94074 22853 94075 22853 1000 2000 "clearline"]
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+	Line[97224 22853 95649 22853 1000 2000 "clearline"]
+	Line[98798 21279 97224 22853 1000 2000 "clearline"]
+	Line[98798 20490 98798 21279 1000 2000 "clearline"]
+	Line[99586 19702 98798 20490 1000 2000 "clearline"]
+	Line[99586 18916 99586 19702 1000 2000 "clearline"]
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+	Line[94074 21278 92500 21278 1000 2000 "clearline"]
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+	Line[97224 18916 96436 18916 1000 2000 "clearline"]
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+	Line[94074 12616 92500 12616 1000 2000 "clearline"]
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+	Line[94861 13404 94861 13403 1000 2000 "clearline"]
+	Line[95649 12616 94861 13404 1000 2000 "clearline"]
+	Line[97224 12616 95649 12616 1000 2000 "clearline"]
+	Line[98011 13403 97224 12616 1000 2000 "clearline"]
+	Line[98011 13404 98011 13403 1000 2000 "clearline"]
+	Line[98798 14191 98011 13404 1000 2000 "clearline"]
+	Line[99586 14191 98798 14191 1000 2000 "clearline"]
+	Line[98799 13404 99586 14191 1000 2000 "clearline"]
+	Line[98798 13404 98799 13404 1000 2000 "clearline"]
+	Line[99586 12616 98798 13404 1000 2000 "clearline"]
+	Line[100373 12616 99586 12616 1000 2000 "clearline"]
+	Line[101161 13404 100373 12616 1000 2000 "clearline"]
+	Line[101948 13404 101161 13404 1000 2000 "clearline"]
+	Line[102735 14191 101948 13404 1000 2000 "clearline"]
+	Line[103523 14191 102735 14191 1000 2000 "clearline"]
+	Line[105098 15766 103523 14191 1000 2000 "clearline"]
+	Line[104311 14979 105098 15766 1000 2000 "clearline"]
+	Line[104310 14979 104311 14979 1000 2000 "clearline"]
+	Line[105098 14191 104310 14979 1000 2000 "clearline"]
+	Line[106672 14191 105098 14191 1000 2000 "clearline"]
+	Line[107460 14979 106672 14191 1000 2000 "clearline"]
+	Line[108247 14979 107460 14979 1000 2000 "clearline"]
+	Line[109034 15766 108247 14979 1000 2000 "clearline"]
+	Line[109035 15766 109034 15766 1000 2000 "clearline"]
+	Line[109822 16553 109035 15766 1000 2000 "clearline"]
+	Line[110609 16553 109822 16553 1000 2000 "clearline"]
+	Line[111397 17341 110609 16553 1000 2000 "clearline"]
+	Line[111397 18128 111397 17341 1000 2000 "clearline"]
+	Line[112184 18915 111397 18128 1000 2000 "clearline"]
+	Line[112184 19703 112184 18915 1000 2000 "clearline"]
+	Line[111397 20490 112184 19703 1000 2000 "clearline"]
+	Line[111397 21278 111397 20490 1000 2000 "clearline"]
+	Line[110610 22065 111397 21278 1000 2000 "clearline"]
+	Line[110609 22065 110610 22065 1000 2000 "clearline"]
+	Line[109822 22852 110609 22065 1000 2000 "clearline"]
+	Line[109822 22853 109822 22852 1000 2000 "clearline"]
+	Line[109035 23640 109822 22853 1000 2000 "clearline"]
+	Line[109035 24427 109035 23640 1000 2000 "clearline"]
+	Line[108247 24427 109035 24427 1000 2000 "clearline"]
+	Line[107459 25215 108247 24427 1000 2000 "clearline"]
+	Line[106672 25215 107459 25215 1000 2000 "clearline"]
+	Line[105097 26790 106672 25215 1000 2000 "clearline"]
+	Line[104310 26790 105097 26790 1000 2000 "clearline"]
+	Line[103523 27577 104310 26790 1000 2000 "clearline"]
+	Line[106672 42538 112184 37026 1000 2000 "clearline"]
+	Text[5400 3200 0 100 "I can wire anything directly into anything" "clearline"]
+	Text[5100 10500 0 100 "I'm the Professor!" "clearline"]
+	Text[91700 90600 0 100 "DrYerzinia" "clearline"]
+	Text[4500 17600 0 100 "PA0RDT Power-Injector r1" "clearline"]
+)
+NetList()
+(
+	Net("GND" "(unknown)")
+	(
+		Connect("C2-1")
+		Connect("C3-1")
+		Connect("PWR-2")
+		Connect("SIGIN-2")
+		Connect("SIGOUT-2")
+	)
+	Net("unnamed_net1" "(unknown)")
+	(
+		Connect("C2-2")
+		Connect("F1-1")
+		Connect("L1-2")
+	)
+	Net("unnamed_net2" "(unknown)")
+	(
+		Connect("C1-1")
+		Connect("L1-1")
+		Connect("SIGIN-1")
+	)
+	Net("unnamed_net3" "(unknown)")
+	(
+		Connect("C1-2")
+		Connect("SIGOUT-1")
+	)
+	Net("unnamed_net4" "(unknown)")
+	(
+		Connect("C3-2")
+		Connect("D1-1")
+		Connect("PWR-1")
+	)
+	Net("unnamed_net5" "(unknown)")
+	(
+		Connect("D1-2")
+		Connect("F1-2")
+	)
+)
+

--- /dev/null
+++ b/PowerInjector/PowerInjector.sch
@@ -1,1 +1,119 @@
+v 20130925 2
+C 41000 51200 1 90 0 inductor-dot-1.sym
+{
+T 40600 51400 5 10 0 0 90 0 1
+device=INDUCTOR
+T 40100 51800 5 10 1 1 0 0 1
+refdes=L1
+T 40400 51400 5 10 0 0 90 0 1
+symversion=0.1
+T 40100 51400 5 10 1 1 0 0 1
+value=470uH
+T 40100 51600 5 10 1 1 0 0 1
+footprint=SRR7032
+}
+C 43500 49500 1 0 1 BNC-1.sym
+{
+T 43600 50100 5 10 1 1 0 0 1
+refdes=SIGOUT
+T 43600 49800 5 10 1 1 0 0 1
+footprint=BNC_LAY
+}
+C 41900 51200 1 90 0 capacitor-1.sym
+{
+T 41200 51400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 41300 51800 5 10 1 1 0 0 1
+refdes=C2
+T 41000 51400 5 10 0 0 90 0 1
+symversion=0.1
+T 41800 51800 5 10 1 1 0 0 1
+footprint=0805
+T 41800 51400 5 10 1 1 0 0 1
+value=100nF
+}
+C 41500 49800 1 0 0 capacitor-1.sym
+{
+T 41700 50500 5 10 0 0 0 0 1
+device=CAPACITOR
+T 41500 50100 5 10 1 1 0 0 1
+refdes=C1
+T 41700 50700 5 10 0 0 0 0 1
+symversion=0.1
+T 42100 49800 5 10 1 1 0 0 1
+footprint=0805
+T 42100 50100 5 10 1 1 0 0 1
+value=100nF
+}
+C 40000 49500 1 0 0 BNC-1.sym
+{
+T 39900 50100 5 10 1 1 0 6 1
+refdes=SIGIN
+T 39900 49800 5 10 1 1 0 6 1
+footprint=BNC_LAY
+}
+N 40500 50000 41500 50000 4
+N 41000 50000 41000 51200 4
+N 42400 50000 43000 50000 4
+C 44700 51200 1 90 0 capacitor-1.sym
+{
+T 44000 51400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 44100 51800 5 10 1 1 0 0 1
+refdes=C3
+T 43800 51400 5 10 0 0 90 0 1
+symversion=0.1
+T 44600 51800 5 10 1 1 0 0 1
+footprint=0805
+T 44600 51400 5 10 1 1 0 0 1
+value=100nF
+}
+C 44000 52800 1 180 0 diode-2.sym
+{
+T 43600 52200 5 10 0 0 180 0 1
+device=DIODE
+T 43600 53000 5 10 1 1 180 0 1
+refdes=D1
+T 43300 52000 5 10 1 1 0 0 1
+footprint=DO214AC
+}
+C 42000 52500 1 0 0 fuse-1.sym
+{
+T 42200 52900 5 10 0 0 0 0 1
+device=FUSE
+T 42000 52600 5 10 1 1 0 0 1
+refdes=F1
+T 42200 53100 5 10 0 0 0 0 1
+symversion=0.1
+T 42500 52200 5 10 1 1 0 0 1
+footprint=ACY200
+T 42300 52700 5 10 1 1 0 0 1
+device=MF-R010
+}
+N 41000 52100 41000 52500 4
+N 41000 52500 42000 52500 4
+N 41700 52100 41700 52500 4
+N 42900 52500 43100 52500 4
+N 44500 52100 44500 52500 4
+N 44000 52500 46000 52500 4
+C 46900 52600 1 180 0 pwrjack-1.sym
+{
+T 46800 52100 5 10 0 0 180 0 1
+device=PWRJACK
+T 46900 52100 5 10 1 1 180 0 1
+refdes=PWR
+T 46300 52700 5 10 1 1 0 0 1
+footprint=GSIP2
+}
+C 45600 51700 1 0 0 gnd-1.sym
+C 44400 50700 1 0 0 gnd-1.sym
+C 41600 50700 1 0 0 gnd-1.sym
+C 43300 49000 1 0 0 gnd-1.sym
+C 40000 49000 1 0 0 gnd-1.sym
+N 40100 49300 40100 49500 4
+N 43400 49300 43400 49500 4
+N 41700 51000 41700 51200 4
+N 44500 51000 44500 51200 4
+N 45700 52000 45700 52300 4
+N 45700 52300 46000 52300 4
 

--- /dev/null
+++ b/PowerInjector/fp/DO214AC.fp
@@ -1,1 +1,10 @@
+Element[0x00000000 "" "" "" 0 0 0 0 0 100 0x00000000]
+(
+	Pad[-8622 -413 -8622 413 7874 4000 8674 "1" "1" 0x00000100]
+	Pad[8622 -413 8622 413 7874 4000 8674 "2" "2" 0x00000100]
+	ElementLine [13543 5512 -13543 5512 1000]
+	ElementLine [-13543 5512 -13543 -5512 1000]
+	ElementLine [-13543 -5512 13543 -5512 1000]
+	ElementLine [13543 -5512 13543 5512 1000]
+)
 

--- /dev/null
+++ b/PowerInjector/fp/GSIP2.fp
@@ -1,1 +1,12 @@
+Element(0x00 "Single in line package" "" "SIP2" 160 10 3 100 0x00)
+(
+	Pin(50 50 66 38 "1" 0x101)
+	Pin(50 150 66 38 "2" 0x01)
+	ElementLine(  0 50   0 150 20)
+	ElementLine(100 50 100 150 20)
+	ElementLine(  0 100 100 100 10)
+	ElementArc(50  50 50 50 180 180 20)
+	ElementArc(50 150 50 50   0 180 20)
+	Mark(50 50)
+)
 

file:b/makefile (new)
--- /dev/null
+++ b/makefile
@@ -1,1 +1,39 @@
 
+.PHONY: build
+
+build: create-dirs all
+
+all: gerb/PA0RDT_Gerb.zip gerb/PowerInjector_Gerb.zip
+
+create-dirs:
+	mkdir -p gerb
+
+gerb/PA0RDT_Gerb.zip:
+	pcb -x gerber --gerberfile gerb/PA0RDT MiniWhip/PA0RDT.pcb
+	mv gerb/PA0RDT.group1.gbr		gerb/PA0RDT.GBL
+	mv gerb/PA0RDT.top.gbr			gerb/PA0RDT.GTL
+	mv gerb/PA0RDT.bottommask.gbr	gerb/PA0RDT.GBS
+	mv gerb/PA0RDT.topmask.gbr		gerb/PA0RDT.GTS
+	mv gerb/PA0RDT.bottomsilk.gbr	gerb/PA0RDT.GBO
+	mv gerb/PA0RDT.topsilk.gbr		gerb/PA0RDT.GTO
+	mv gerb/PA0RDT.outline.gbr		gerb/PA0RDT.GKO
+	mv gerb/PA0RDT.plated-drill.cnc	gerb/PA0RDT.XLN
+	zip gerb/PA0RDT_Gerb.zip gerb/PA0RDT.GBL gerb/PA0RDT.GTL gerb/PA0RDT.GBS gerb/PA0RDT.GTS gerb/PA0RDT.GBO gerb/PA0RDT.GTO gerb/PA0RDT.GKO gerb/PA0RDT.XLN
+	rm gerb/PA0RDT.*
+
+gerb/PowerInjector_Gerb.zip:
+	pcb -x gerber --gerberfile gerb/PowerInjector PowerInjector/PowerInjector.pcb
+	#mv gerb/PowerInjector.group1.gbr		gerb/PowerInjector.GBL
+	mv gerb/PowerInjector.top.gbr			gerb/PowerInjector.GTL
+	mv gerb/PowerInjector.bottommask.gbr	gerb/PowerInjector.GBS
+	mv gerb/PowerInjector.topmask.gbr		gerb/PowerInjector.GTS
+	mv gerb/PowerInjector.bottomsilk.gbr	gerb/PowerInjector.GBO
+	mv gerb/PowerInjector.topsilk.gbr		gerb/PowerInjector.GTO
+	mv gerb/PowerInjector.outline.gbr		gerb/PowerInjector.GKO
+	mv gerb/PowerInjector.plated-drill.cnc	gerb/PowerInjector.XLN
+	zip gerb/PowerInjector_Gerb.zip gerb/PowerInjector.GBL gerb/PowerInjector.GTL gerb/PowerInjector.GBS gerb/PowerInjector.GTS gerb/PowerInjector.GBO gerb/PowerInjector.GTO gerb/PowerInjector.GKO gerb/PowerInjector.XLN
+	rm gerb/PowerInjector.*
+
+clean:
+	rm -rf gerb
+